WCFS1016V1C Datasheet, PDF (4/9 Pages) Weida Semiconductor, Inc. – 64K x 16 Static RAM

WCFS1016V1C
Switching Characteristics^[4] Over the Operating Range
Parameter
READ CYCLE
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
WRITE CYCLE^[7]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_LZWE
t_HZWE
t_BW
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z^{[5, 6]}
CE LOW to Low Z^[6]
CE HIGH to High Z^{[5, 6]}
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z^[6]
WE LOW to High Z^{[5, 6]}
Byte Enable to End of Write
WCFS1016V1C 12ns
Min.
Max.
Unit
12
ns
12
ns
3
ns
12
ns
6
ns
0
ns
6
ns
3
ns
6
ns
0
ns
12
ns
6
ns
0
ns
6
ns
12
ns
9
ns
8
ns
0
ns
0
ns
8
ns
6
ns
0
ns
3
ns
6
ns
8
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions^[8]
Min.
Max.
Unit
V_DR
V_CC for Data Retention
2.0
V
t_CDR[9]
Chip Deselect to Data Retention Time V_CC = V_DR = 2.0V,
0
ns
t_R[10]
Operation Recovery Time
CE > V_CC – 0.3V,
V_IN > V_CC – 0.3V or V_IN < 0.3V
t_RC
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 30-pF load capacitance.
5. t_HZOE, t_HZBE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. No input may exceed V_CC + 0.5V.
9. Tested initially and after any design or process changes that may affect these parameters.
10. t_r < 3 ns for the -12 and -15 speeds. t_r < 5 ns for the -20 and slower speeds.
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