WCFS1008C3E Datasheet, PDF (4/8 Pages) Weida Semiconductor, Inc. – 128K x 8 Static RAM

WCFS1008C3E
WCFS1008C9E
Data Retention Characteristics Over the Operating Range
Parameter
Description
V_DR
t_CDR
t_R
V_CC for Data Retention
Chip Deselect to Data Retention Time
Operation Recovery Time
Conditions
No input may exceed V_CC + 0.5V
V_CC = V_DR = 2.0V,
CE₁ > V_CC – 0.3V or CE₂ < 0.3V,
V_IN > V_CC – 0.3V or V_IN < 0.3V
Data Retention Waveform
Min. Max Unit
2.0
V
0
ns
200
µs
DATA RETENTION MODE
V_CC
4.5V
V_DR > 2V
4.5V
t_CDR
t_R
CE
Switching Waveforms
Read Cycle No. 1^{[10, 11]}
t_RC
ADDRESS
DATA OUT
t_AA
t_OHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)^{[11, 12]}
ADDRESS
t_RC
CE₁
CE₂
OE
DATA OUT
V_CC
SUPPLY
CURRENT
t_ACE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
Note:
10. Device is continuously selected. OE, CE₁ = V_IL, CE₂ = V_IH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE₁ transition LOW and CE₂ transition HIGH.
DATA VALID
t_HZOE
t_HZCE
HIGH
IMPEDANCE
t_PD
I_CC
50%
I_SB
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