WCFS1008C3E Datasheet, PDF (3/8 Pages) Weida Semiconductor, Inc. – 128K x 8 Static RAM

WCFS1008C3E
WCFS1008C9E
AC Test Loads and Waveforms
R1 480Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 480Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Switching Characteristics^[5] Over the Operating Range
WCFS1008C3E
WCFS1008C9E-15
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t_RC
Read Cycle Time
15
ns
t_AA
Address to Data Valid
15
ns
t_OHA
Data Hold from Address Change
3
ns
t_ACE
CE₁ LOW to Data Valid, CE₂ HIGH to Data Valid
15
ns
t_DOE
OE LOW to Data Valid
7
ns
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Low Z
OE HIGH to High Z^{[6, 7]}
CE₁ LOW to Low Z, CE₂ HIGH to Low Z^[7]
CE₁ HIGH to High Z, CE₂ LOW to High Z^{[6, 7]}
0
ns
7
ns
3
ns
7
ns
t_PU
CE₁ LOW to Power-Up, CE₂ HIGH to Power-Up
0
ns
t_PD
CE₁ HIGH to Power-Down, CE₂ LOW to Power-Down
WRITE CYCLE^[8]
15
ns
t_WC
Write Cycle Time^[9]
15
ns
t_SCE
CE₁ LOW to Write End, CE₂ HIGH to Write End
12
ns
t_AW
Address Set-Up to Write End
12
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-Up to Write Start
0
ns
t_PWE
WE Pulse Width
12
ns
t_SD
Data Set-Up to Write End
8
ns
t_HD
t_LZWE
t_HZWE
Data Hold from Write End
WE HIGH to Low Z^[7]
WE LOW to High Z^{[6, 7]}
0
ns
3
ns
7
ns
Note:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 30-pF load capacitance.
6. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD
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