W3HG2128M72ACER-AD6 Datasheet, PDF (9/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP

White Electronic Designs ^{W3HG2128M72ACER-AD6}
PRELIMINARY
Notes
1. All voltages referenced to VSS
2. Tests for AC timing, ICC, and electrical AC and DC characteristics
may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
VTT = VCCQ/2
25Ω
Output
(VOUT)
Reference
Point
4. AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V
in the test environment parameter specifications are guaranteed
for the specified AC input levels under normal use conditions. The
minimum slew rate for the input signals used to test the device is
1.0V/ns for signals in the range between VIL (AC) and VIH (AC).
Slew derates less than 1.0V/ns require the timing parameters to be
rated as specified.
5. The AC and DC input level specifications are as defined in the
SSTL_18 standard (i.e., the receiver will effectively switch as a
result of the signal crossing the AC input level and will remain in
that state as long as the signal does not ring back above [below]
the DC input LOW [HIGH] level).
6. Command/Address minimum input slew rate is at 1.0V/ns.
Command/Address input timing must be derated if the slew rate is
not 1.0V/ns. This is easily accommodated using tISb and the Setup
and Hold Time Derating Values table. tIS timing (tISb) is referenced
from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH
timing (tIHb) is referenced from VIH (AC) for a rising signal and VIL
(DC) for a falling signal. The timing table also lists the tISb and tIHb
values for a 1.0V/ns slew rate; these are the “base” values.
7. Data minimum input slew rate is at 1.0V/ns. Data input timing
must be derated if the slew rate is not 1.0V/ns. This is easily
accommodated if the timing is referenced from the logic trip points.
tDS timing (tDSb) is referenced from VIH (AC) for a rising signal and
VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH
(DC) for a rising signal and VIL (DC) for a falling signal. The timing
table lists the tDSb and tDHb values for a 1.0V/ns slew rate. If the
DQS/DQS# differential strobe feature is not enabled, timing is no
longer referenced to the cross point of DQS/DQS#. Data timing
is now referenced to VREF, provided the DQS slew rate is not less
than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data
timing is now referenced to VIH (AC) for a rising DQS and VIL (DC)
for a falling DQS.
8. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (when the device output is no longer driving (tHZ) or
begins driving (tLZ).
9. This maximum value is derived from the referenced test load. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
10. tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX)
condition.
11. The intent of the Don’t Care state after completion of the
postamble is the DQS-driven signal should either be high, low or
High-Z and that any signal transition within the input switching
region must follow valid input requirements. That is if DQS
transitions high (above VIH DC (MIN) then it must not transition low
(below VIH (DC) prior to tDQSH (MIN).
12. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus turn
around.
13. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on tDQSS.
14. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, a REFRESH command must be
asserted at least once every 70.3µs or tRFC (MAX). To ensure
all rows of all banks are properly refreshed, 8192 REFRESH
commands must be issued every 64ms.
15. Each half-byte lane has a corresponding DQS.
16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured
differentially).
17. The data valid window is derived by achieving other specifications
- tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty cycle and a practical
data valid window can be derived.
18. MIN (tCL, tCH) refers to the smaller of the actual clock low time and
the actual clock high time as provided to the device (i.e. This value
can be greater than the minimum specification limits for tCL and
tCH. For example, tCL and tCH are = 50 percent of the period, less
the half period jitter [tJIT(HP)] of the clock source, and less the half
period jitter due to cross talk [tJIT(cross talk)] into the clock traces.
19. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually
applied to the device CK and CK# inputs.
20. READs and WRITEs with auto precharge are allowed to be
issued before tRAS (MIN) is satisfied since tRAS lockout feature is
supported in DDR2 SDRAM devices.
21. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb or 1Gb
DDR2 SDRAM data sheet for more detail.
22. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already
an integer, round to the next highest integer. tCK refers to the
application clock period; nWR refers to the tWR parameter stored
in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR
programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 +
(4) clocks = 8 clocks.
23. The minimum READ to internal PRECHARGE time. This
parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) ≤ 1,
then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has
to be satisfied as well. The DDR2 SDRAM device will automatically
delay the internal PRECHARGE command until tRAS (MIN) has
been satisfied.
24. Operating frequency is only allowed to change during self refresh
mode, precharge power-down mode, and system reset condition.
25. ODT turn-on time tAON (MIN) is when the device leaves high
impedance and ODT resistance begins to turn on. ODT turn-on
time tAON (MAX) is when the ODT resistance is fully on. Both are
measured from tAOND.
May 2006
Rev. 5
9
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