W3HG2128M72ACER-AD6 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP

White Electronic Designs ^{W3HG2128M72ACER-AD6}
PRELIMINARY
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
806
Operating one bank active-precharge current;
ICC0 tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; TBD
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
ICC1
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD =
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
TBD
Data pattern is same as ICC4W
Precharge power-down current;
ICC2P All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
TBD
bus inputs are FLOATING
Precharge quiet standby current;
ICC2Q All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
TBD
STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
TBD
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
TBD
ICC3P ^{All banks open; tCK = tCK(ICC); CKE is LOW; Other control and}
address bus inputs are STABLE; Data bus inputs are FLOATING ^{Slow PDN Exit MRS(12) = 1}
TBD
Active standby current;
ICC3N
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
TBD
SWITCHING
Operating burst write current;
ICC4W
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
TBD
are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
ICC4R
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
TBD
are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
ICC5B tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid TBD
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
ICC6 CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
TBD
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
ICC7 tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; TBD
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
NOTE: ICC specs are based on MICRON components. Other DRAM manufacturers parameters may be different.
665 534 403 Units
1,720 1,530 1,530 mA
1,980 1,800 1,710 mA
180 180 180 mA
1,800 1,440 1,260 mA
1,980 1,620 1,440 mA
1,260 1,080 900 mA
360 360 360 mA
2,340 1,980 1,620 mA
2,880 2,430 2,070 mA
3,240 2,700 2,160 mA
7,560 7,200 6,840 mA
180 180 180 mA
5,130 4,770 4,230 mA
May 2006
Rev. 5
5
White Electronic Designs Corporation • [phone] • www.wedc.com