W3HG2128M72ACER-AD6 Datasheet, PDF (6/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP

White Electronic Designs ^{W3HG2128M72ACER-AD6}
PRELIMINARY
AC TIMING PARAMETERS
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
667
534
403
PARAMETER
Clock cycle time
CK high-level width
CK low-level width
Half clock period
CL = 6
CL = 5
CL = 4
CL = 3
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
SYMBOL MIN
tCK (6)
TBD
tCK (5)
TBD
tCK (4)
TBD
tCK (3)
TBD
tCH
TBD
tCL
TBD
tHP
TBD
tAC
TBD
tHZ
TBD
MAX MIN MAX MIN MAX MIN MAX UNIT Notes
TBD
ps 16, 24
TBD 3,000 8,000
ps 16, 24
TBD 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24
TBD 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24
TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18
TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18
MIN
MIN
MIN
TBD
(tCH,
(tCH,
(tCH,
tCL)
tCL)
tCL)
ps 19
TBD -450 +450 -500 +500 -600 +600 ps
tAC
tAC
tAC
ps
8, 9
TBD
(MAX)
MAX
MAX
Data-out low-impedance window from CK/CK# tLZ
tAC
tAC
tAC
tAC
tAC
tAC
ps 8, 10
TBD TBD _{(MIN) (MAX) (MIN) (MAX) (MIN) (MAX)}
DQ and DM input setup time relative to DQS
tDSa
300
350
400
TBD
TBD
ps 7, 15,
21
DQ and DM input hold time relative to DQS
tDHa
300
350
400
TBD
TBD
ps 7, 15,
21
DQ and DM input setup time relative to DQS
tDSb
100
100
150
tCK 7, 15,
TBD
TBD
21
DQ and DM input hold time relative to DQS
tQHb
175
225
275
TBD
TBD
ps 7, 15,
21
DQ…DQS hold, DQS to first DQ to go
tDIPW
0.35
0.35
0.35
ps
nonvalid, per access relative to DQS
TBD
TBD
Data hold skew factor
tQHS
TBD
TBD
340
400
450
DQ–DQS hold, DQS to first DQ to go nonvalid, tQH
tHP-
tHP-
tHP-
per access
TBD
TBD
tQHS
tQHS
tQHS
15, 17
Data valid output window (DVW)
tDVW
tQH-
TBD
TBD
tDQSQ
tQH-
tDQSQ
tQH-
tDQSQ
15, 17
DQS input high pulse width
tDQSH
TBD
TBD 0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
TBD
TBD 0.35
0.35
0.35
tCK
DQS output access time from CK/CK#
tDQSCK TBD TBD -400 +400 -450 +450 -500 +500 ps
DQS falling edge to CK rising– setup time
tDSS
0.2
0.2
0.2
tCK
TBD
TBD
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
tCK
TBD
TBD
DQS–DQ skew, DQS to last DQ valid, per
tDQSQ
240
300
350 ps 15, 17
group, per access
TBD
TBD
DQS read preamble
tRPRE
TBD TBD 0.9 1.1 0.9 1.1 0.9 1.1
tCK
35
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
May 2006
Rev. 5
6
White Electronic Designs Corporation • [phone] • www.wedc.com