W3EG7264S-AD4 Datasheet, PDF (9/13 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
3. Outputs (except for IDD measurements) measured with equivalent load:
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VCC/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VCC/2, VREF is allowed ±25mV for
DC error and an additional ±25mV for AC noise. This measurement is to be taken at
the nearest VREF bypass capacitor.
7. VTT is not applied directly to the device. VTT, a system supply for signal termination
resistors, is expected to be set equal to VREF and must track variations in the DC
level of VREF.
8. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
9. The value of VIX and VMP are expected to equal VCC/2 of the transmitting device and
must track variations in the DC level of the same.
10. IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle times at CL = 2.5 for 335, and CL = 2 for 262, 265 and 202
speeds with the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly initialized and is averaged at
the defined cycle rate.
13. This parameter is sampled. VCC = +2.5V±0.2V, VCC = +2.5V±0.2V, VREF = VSS, f =
100 MHz, TA = 25°C, VOUT (DC) = VCC/2, VOUT (peak to peak) = 0.2V. DM input is
grouped with I/O pins, reflecting that they are matched in loading.
14. For slew rates < 1 V/ns and ≥ 0.5 V/ns. If slew rate is less than 0.5 V/ns, timing
must be derated; tIS has an additional 50ps per each 100mV/ns reduction in slew
rate from the 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For 335, slew rates must be greater than or equal to
0.5V/ns.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including
Self-Refresh mode, VREF must be powered within the specified range. Exception:
during the period before VREF stabilizes, CKE = 0.3 x VCC is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as data valid
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the “Don’t Care” state after completion of the postamble is that the
DQS-driven signal should either be HIGH, LOW, or High-Z and that any signal
transition within the input switching region must follow valid input requirements. If
DQS transitions HIGH, above DC VIH (MIN) then it must not transition LOW, below
DC VIH, prior to tDQSH (MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
22. tRC (MIN) or tRFC (MIN) for IDD measurements is the smallest multiple of tCK that
meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maxi-mum absolute value
for tRAS.
23. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
25. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ,
and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the
clock duty cycle and a practical data valid window can be derived. The clock is
allowed a maximum duty-cycle variation of 45/55, because functionality is uncertain
when operating beyond a 45/55 ratio.
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with
DQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
27. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
28. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL (DC) or VIH (DC).
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must
be added to tDS and tDH for each 0.1 V/ns reduction in slew rate. For 335 speed
grades, slew rate must be ≥ 0.5 V/ns. If slew rate exceeds 4 V/ns, functionality is
uncertain.
32. VCC must not vary more than four percent if CKE is not active while any bank is
active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS
(MIN) can be satisfied prior to the internal PRECHARGE command being issued.
January 2005
Rev. 3
9
White Electronic Designs Corporation • [phone] • www.wedc.com