W3EG7264S-AD4 Datasheet, PDF (10/13 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY
36. Any positive glitch must be less than 1/3 of the clock cycle and not more than
+400mV or 2.9V. Any negative glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V.
37. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
38. VIH overshoot: VIH (MAX) = VCC + 1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL under-shoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
39. VCC and VCC must track each other.
40. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
41. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
42. During initialization, VCC, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power-up, even if VCC/VCC are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply
and the input pin.
43. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
44. When an input signal is indicated to be HIGH or LOW, it is defined as a steady state
logic HIGH or LOW.
45. Random addressing changing; 50 percent of data changing at every transfer.
46. Random addressing changing; 100 percent of data changing at every transfer.
47. CKE must be active (HIGH) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
48. IDD2N specifies the DQ, DQS and DM to be driven to a valid HIGH or LOW logic
level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs
to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
49. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
50. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC voltage range of 2.6V±100mV.
51. The 335 speed grades will operate with tRAS(min) = 40ns and tRAS(max) = 120,000ns
at any slower frequency.
January 2005
Rev. 3
10
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