W3EG7264S-AD4 Datasheet, PDF (7/13 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265
202
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command
period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tAC -0.7 +0.7 +0.75 -0.75 +0.75 -0.75 +0.75 -0.75 ns
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 25
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 25
tCK (2.5) 7.6
13
10
13
10
13
10
13
ns 37, 42
tCK (2)
7.5
13
7.5
13
7.5
13
7.5
13
ns
41
tDH 0.45
ns 22, 26
tDS
0.45
ns 22, 26
tDIPW 1.75
ns 26
tDQSCK -0.60 +0.60 +0.8
+0.8
+0.8
ns
tDQSH 0.35
tCK
tDQSL 0.35
tCK
tDQSQ
0.45
0.6
0.6
0.6 ns 22
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25
tDSS
0.2
0.2
0.2
0.2
tDSH
0.2
0.2
0.2
0.2
tHP
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
tHZ
+0.70
+0.8
+0.8
+0.8
tLZ -0.70
-0.8
-0.8
-0.8
tIHF
0.75
ns 12 ns 12 ns 12
tISF
0.75
1.1
1.1
1.1
tIHS
0.80
1.1
1.1
1.1
tISS
0.80
1.1
1.1
1.1
tIPW
2.2
2.2
2.2
2.2
tMRD
12
16
16
16
tQH tHP - tQHS
tHP - tQHS
tHP - tQHS
tHP - tQHS
tCK
tCK
tCK
ns 29
ns 16, 36
ns 16, 36
ns 12
ns 12
ns 12
ns 12
ns
ns
ns 22
tQHS
0.55
1
1
1
ns
tRAS 42 70,000 40 120,000 40 120,000 40 120,000 ns 30
tRAP
15
20
20
20
ns
tRC
60
70
70
70
ns
tRFC
72
75
75
75
tRCD
15
20
20
20
tRP
15
20
20
20
tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1
tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
tRRD
12
15
15
15
tWPRE 0.25
0.25
0.25
0.25
tWPRES
0
0
0
0
ns 40
ns
ns
tCK
tCK
ns
tCK
ns 17, 19
January 2005
Rev. 3
7
White Electronic Designs Corporation • [phone] • www.wedc.com