W3EG6433S-D3 Datasheet, PDF (9/12 Pages) White Electronic Designs Corporation – 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6433S-D3
-JD3
PRELIMINARY
Notes
1. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output in no
longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at
some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate
specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from High- Z to logic
LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending
on tDQSS.
4. A maximum of eight AUTO REFRESH commands can be posted
to any given DDR SDRAM device.
5. For command/address input slew rate ≥ 1.0 V/ns.
6. For command/address input slew rate ≥ 0.5 V/ns and > 1.0 V/ns
7. For CK & CK# slew rate ≥ 1.0 V/ns.
8. These parameters guarantee device timing, but they are not
necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac).
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and
the actual clock high time as provided to the device (i.e. this value
can be greater than the minimum specification limits for tCL and
tCH. For example, tCL and tCH are = 50% of the period, less the half
period jitter (tJIT(HP)) of the clock source, and less the half period
jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
11. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined
by clock high or clock low tCH, tCL). tQHS accounts for 1) The pulse
duration distortion of on-chip clock circuits; and 2) The worst case
push-out of DQS on one transition followed by the worst case
pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
12. tDQSQ
Consists of data pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers for any given cycle.
13. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to
the next highest integer. Example: For DDR266 at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL =
5 clocks
November 2005
Rev. 2
9
White Electronic Designs Corporation • [phone] • www.wedc.com