W3EG6433S-D3 Datasheet, PDF (7/12 Pages) White Electronic Designs Corporation – 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6433S-D3
-JD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC Characteristics
335
262
263
265
(DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5)
Parameter
Symbol Min Max Min Max Min Max Min Max
Row cycle time
tRC
60
60
65
65
Refresh row cycle time
tRFC
72
75
75
75
Row active time
tRAS
42
70K
45 120K 45 120K 45 120K
RAS to CAS delay
tRCD
18
15
20
20
Row precharge time
tRP
18
15
20
20
Row active to Row active delay
tRRD
12
15
15
15
Write recovery time
tWR
15
15
15
15
Last data in to Read command
tWTD
1
1
1
1
Col. address to Col. address delay
tCCD
1
1
1
1
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
7.5
12
10
12
CL=2.5
6
12
7.5
12
7.5
12
7.5
12
Clock high level width
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
Clock low level width
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
DQS-out access time from CK/CK
tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75
Output data access time from CK/CK
tAC
-0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75
Data strobe edge to output data edge
tDQSQ
-
0.45
-
0.5
-
0.5
-
0.5
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK to valid DQS-in
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25
DQS-in setup time
tWPRES
0
0
0
0
DQS-in hold time
tWPRE 0.25
0.25
0.25
0.25
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
0.2
DQS falling edge from Ck rising-hold time
tDSH
0.2
0.2
0.2
0.2
DQS-in high level width
tDQSH 0.35
0.35
0.35
0.35
DQS-in low level width
tDQSL 0.35
0.35
0.35
0.35
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
Address and Control Input setup time (fast)
tIS
0.75
0.9
0.9
0.9
Address and Control Input hold time (fast)
tIH
0.75
0.9
0.9
0.9
Address and Control Input setup time (slow)
tIS
0.8
1.0
1.0
1.0
Address and Control Input setup time (slow)
tIH
0.8
1.0
1.0
1.0
Data-out high impedence time from CK/CK
tHZ
+0.7
+0.75
+0.75
+0.75
Data-out high impedence time from CK/CK
tLZ
-0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75
Input Slew Rate (for input only pins)
tSL(I)
0.5
0.5
0.5
0.5
Input Slew Rate (for I/O pins)
tSL(IO)
0.5
0.5
0.5
0.5
Units
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
V/ns
V/ns
Notes
12
3
i,5.7~9
i,5.7~9
i,6~9
i,6~9
1
1
November 2005
Rev. 2
7
White Electronic Designs Corporation • [phone] • www.wedc.com