W3EG6433S-D3 Datasheet, PDF (6/12 Pages) White Electronic Designs Corporation – 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6433S-D3
-JD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR333@CL=2.5
Max
DDR266@CL=2
Max
Operating Current
IDD0 One device bank; Active - Precharge;
680
640
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
880
800
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down
24
24
Down Standby
mode; tCK=tCK (MIN); CKE=(low)
Current
Idle Standby Current IDD2F CS# = High; All device banks idle;
200
180
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down IDD3P One device bank active; Power-Down
240
200
Standby Current
mode; tCK (MIN); CKE=(low)
Active Standby
IDD3N CS# = High; CKE = High; One device
360
320
Current
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
1,120
960
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
1,160
1,000
Auto Refresh
Current
IDD5 tRC = tRC (MIN)
1,320
1,240
Self Refresh Current IDD6 CKE ≤ 0.2V
16
16
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
2,400
2,000
NOTES:
• Module IDD was calculated on the basis of component IDD and can be different measured according to dq hearing cap.
• IDD specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
DDR266@CL=2/2.5
Max
640
Units
mA
800
mA
24
rnA
180
mA
200
mA
320
mA
960
mA
1,000
rnA
1,240
mA
16
mA
2,000
mA
November 2005
Rev. 2
6
White Electronic Designs Corporation • [phone] • www.wedc.com