W3EG72128S-AD4 Datasheet, PDF (8/14 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
AC CHARACTERISTICS
335
262
265/202
PARAMETER
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
SYMBOL MIN MAX
tISS
0.8
tIPW
2.2
tMRD
12
tQH
tHP - tQHS
tQHS
0.50
tRAS
42 70,000
tRAP
15
tRC
60
tRFC
72
tRCD
15
tRP
15
tRPRE
0.9
1.1
tRPST
0.4
0.6
tRRD
12
tWPRE
0.25
tWPRES
0
tWPST
0.4
0.6
tWR
15
tWTR
1
NA
tQH -tDQSQ
tREFC
70.3
tREFI
7.8
tVTD
0
tXSNR
75
tXSRD
200
MIN MAX MIN MAX
1
1
2.2
2.2
15
15
tHP - tQHS
tHP - tQHS
0.75
0.75
40 120,000 40 120,000
15
20
60
65
75
78
15
20
15
20
0.9
1.1
0.9
1.1
0.4
0.6
0.4
0.6
15
15
0.25
0.25
0
0
0.4
0.6
0.4
0.6
15
15
1
1
tQH -tDQSQ
tQH - tDQSQ
70.3
70.3
7.8
7.8
0
0
75
75
200
200
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
ns
ns
tCK
NOTES
12
22, 23
30, 47
42
37
37
18, 19
17
22
21
21
August 2005
Rev. 3
8
White Electronic Designs Corporation • [phone] • www.wedc.com