W3EG72128S-AD4 Datasheet, PDF (7/14 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
SYMBOL
tAC
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
MIN MAX
-0.70 +0.70
0.45 0.55
0.45 0.55
6
13
7.5
13
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.4
0.75 1.25
0.20
0.20
tCH,tCL
+0.70
-0.70
0.75
0.75
0.8
MIN MAX MIN MAX UNITS NOTES
-0.75 +0.75 -0.75 0.75
ns
0.45 0.55 0.45 0.55
tCK
26
0.45 0.55 0.45 0.55
tCK
26
7.5
13
7.5
13
ns 39, 44
7.5
13 7.5/10 13
ns 39, 44
0.5
0.5
ns 23, 27
0.5
0.5
ns 23, 27
1.75
1.75
ns
27
-0.75 +0.75 -0.75 +0.75 ns
0.35
0.35
tCK
0.35
0.35
tCK
0.5
0.5
ns 22, 23
0.75
1.25
0.75
1.25
tCK
0.20
0.2
tCK
0.20
0.2
tCK
tCH,tCL
tCH, tCL
ns
30
+0.75
+0.75 ns 16, 36
-0.75
-0.75
ns 16, 36
0.90
0.90
ns
12
0.90
0.90
ns
12
1
1
ns
12
August 2005
Rev. 3
7
White Electronic Designs Corporation • [phone] • www.wedc.com