W3EG72128S-AD4 Datasheet, PDF (5/14 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2
Max
Max
Max
Max
Units
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM
Operating Current
IDD0
and DQS inputs changing once per
clock cycle; Address and control
2620
2620
2620
2620
mA
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge; Burst = 2; tRC=tRC(MIN)
Operating Current
IDD1 ;tCK=tCK(MIN); Iout = 0mA; Address
2890
2890
2890
2890
mA
and control inputs changing once per
clock cycle.
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power- down
mode; tCK=tCK(MIN); CKE=(low)
90
90
90
90
mA
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address
Idle Standby Current IDD2F and other control inputs changing
1085
1085
1085
1085
mA
once per clock cycle. Vin = Vref for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down
mode; tCK(MIN); CKE=(low)
630
630
630
630
mA
CS# = High; CKE = High; One
device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ,
Active Standby Current IDD3N DM and DQS inputs changing twice
1175
1175
1175
1175
mA
per clock cycle; Address and other
control inputs changing once per
clock cycle.
Burst = 2; Reads; Continous burst;
One device bank active;Address
Operating Current
IDD4R and control inputs changing once
2935
2935
2935
2935
mA
per clock cycle; tCK=tCK(MIN); Iout
= 0mA.
Burst = 2; Writes; Continous burst;
One device bank active; Address
Operating Current
IDD4W
and control inputs changing once per
clock cycle; tCK=tCK(MIN); DQ,DM
3025
2845
2845
2845
mA
and DQS inputs changing twice per
clock cycle.
Auto Refresh Current IDD5 tRC=tRC(MIN)
4060
4060
4060
4060
mA
Self Refresh Current
IDD6 CKE ≤ 0.2V
360
365
365
365
mA
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
Operating Current
IDD7A (MIN); tCK=tCK(MIN); Address and
5095
5050
5050
5050
mA
control inputs change only during
Active Read or Write commands.
August 2005
Rev. 3
5
White Electronic Designs Corporation • [phone] • www.wedc.com