W3EG2128M72AFSR-D3 Datasheet, PDF (7/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA

W3EG2128M72AFSR-D3
White Electronic Designs
-AD3
FINAL
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262
265
Parameter
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
Clock cycle time
CL=3
CL=2.5
CL=2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time
(slew rate >/ =.5V/ns)
Symbol Min
tAC -0.70
tCH 0.45
tCL 0.45
tCK (3) 5
tCK (2.5) 6
tCK (2) 7.5
tDH 0.40
tDS 0.40
tDIPW 1.75
tDQSCK -0.60
tDQSH 0.35
tDQSL 0.35
tDQSQ
Max
+0.70
0.55
0.55
7.5
12
12
+0.60
0.40
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHf
0.72
0.2
0.2
tCH, tCL
-0.70
0.60
1.28
+0.70
Min Max
-0.70 +0.70
0.45 0.55
0.45 0.55
6
13
6
12
7.5 12
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.45
0.75 1.25
0.2
0.2
tCH, tCL
+0.70
-0.70
0.75
Min Max
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5 13
7.5 12
7.5 12
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
0.90
Min
-0.75
0.45
0.45
7.5
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
0.75
0.2
0.2
tCH, tCL
-0.75
0.90
Max
+0.75
0.55
0.55
13
12
12
+0.75
0.5
1.25
+0.75
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
Notes
16
16
22
22
22
14,17
14,17
17
13,14
18
8,19
8,20
6
Address and control input set-up time
(slew rate >/ =.5V/ns)
tISf 0.60
0.75
0.90
0.90
ns
6
Address and control input hold time (slow slew rate)
tIHs N/A
0.80
1
1
ns
6
Address and control input setup time (slow slew rate)
tISs N/A
0.80
1
1
ns
6
Address and control input pulse width (for each input) tIPW 2.2
2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
12
15
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
ns 13,14
Data hold skew factor
tQHS
0.55
0.55
0.75
0.75 ns
ACTIVE to PRECHARGE command
tRAS 40 70,000 42 70,000 40 120,000 40 120,000 ns 15
ACTIVE to READ with Auto precharge command
tRAP
15
15
15
15
ns
Note:
• These parameters serve to support both SAMSUNG and MICRON components based modules.
Continued on next page
January 2006
Rev. 3
7
White Electronic Designs Corporation • [phone] • www.wedc.com