W3EG2128M72AFSR-D3 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA

W3EG2128M72AFSR-D3
White Electronic Designs
-AD3
FINAL
ICC SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Parameter
Rank 1
Symbol Conditions
DDR400@CL=3
Max
Operating Current
ICC0 One device bank; Active - Precharge; tRC = tRC (MIN);
3870
tCK = tCK (MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
Operating Current
ICC1 One device bank; Active-Read-Precharge Burst = 2;
4410
tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per clock cycle.
Precharge Power-
ICC2P All device banks idle; Power-down mode; tCK = tCK
180
Down Standby
(MIN); CKE = (low)
Current
Idle Standby
ICC2F CS# = High; All device banks idle;
1980
Current
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN =
VREF for DQ, DQS and DM.
Active Power-Down ICC3P One device bank active; Power-Down mode; tCK
1620
Standby Current
(MIN); CKE = (low)
Active Standby
ICC3N CS# = High; CKE = High; One device bank; Active-
2160
Current
Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
Operating Current
ICC4R Burst = 2; Reads; Continuous burst; One device bank
4500
active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); lOUT = 0mA.
Operating Current ICC4W Burst = 2; Writes; Continuous burst; One device bank
4590
active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
Auto Refresh
ICC5 tRC = tRC (MIN)
7290
Current
Self Refresh
ICC6 CKE ≤ 0.2V
180
Current
Operating Current
ICC 7A Four bank interleaving Reads (BL=4) with auto
9180
precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address
and control inputs change only during Active Read or
Write commands.
Note:
• These parameters serve to support both SAMSUNG and MICRON components based modules.
DDR333@CL=2.5
Max
2780
3780
180
1620
1260
1800
3870
4050
6120
180
8190
DDR266@CL=2,
2.5
Max
2790
3780
180
1620
1260
1800
3870
3690
6120
180
8100
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
Rank 2
Standby
State
ICC3N
ICC3N
ICC2P
ICC2F
ICC3P
ICC3N
ICC3N
ICC3N
ICC3N
ICC6
ICC3N
January 2006
Rev. 3
5
White Electronic Designs Corporation • [phone] • www.wedc.com