W3EG2256M72ASSR-JD3 Datasheet, PDF (6/14 Pages) White Electronic Designs Corporation – 4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL

White Electronic Designs
W3EG2256M72ASSR-JD3
-AJD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes PLL and register power
Parameter
Rank 1
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge; tRC = tRC
(MIN); tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and
control inputs changing once every two cycles.
Operating Current
IDD1 One device bank; Active-Read-Precharge Burst
= 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down mode; tCK =
Down Standby Current
tCK (MIN); CKE = (low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN
= VREF for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
Active Standby Current IDD3N CS# = High; CKE = High; One device bank;
Active-Precharge;tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
Auto Refresh Current
IDD5 tRC = tRC (MIN)
Self Refresh Current
IDD6 CKE ≤ 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only during
Active Read or Write commands.
DDR266:@CL=2, 2.5
Max
5265
5895
360
2650
1260
2110
6345
6525
8540
599
11835
DDR200@CL=2
Max
4815
5445
360
2470
1080
1930
5805
5985
8180
599
10935
Units
mA
Rank 2
Standby
State
IDD3N
mA
IDD3N
rnA
IDD2P
mA
IDD2F
mA
IDD3P
mA
IDD3N
mA
IDD3N
rnA
IDD3N
mA
IDD3N
mA
IDD6
mA
IDD3N
November, 04
Rev. 3
6
White Electronic Designs Corporation • [phone] • www.wedc.com