W3EG72256S-JD3 Datasheet, PDF (5/14 Pages) White Electronic Designs Corporation – 2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL

White Electronic Designs
W3EG72256S-JD3
-AJD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
Down Standby
Current
IDD2P All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current IDD2F CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
Active Standby
Current
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh
Current
IDD5 tRC = tRC (MIN)
Self Refresh Current IDD6 CKE ≤ 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR333@CL=2.5*
Max
2880
3510
180
1170
630
900
3960
4140
6120
162
9450
DDR266@CL=2, 2.5
Max
2610
3240
180
1080
540
810
3600
3780
5940
162
8730
DDR200@CL=2
Max
2610
3240
180
1080
540
810
3600
3780
5940
162
8730
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
December 2004
Rev. 2
5
White Electronic Designs Corporation • [phone] • www.wedc.com