W3E32M72SR-XSBX Datasheet, PDF (4/19 Pages) White Electronic Designs Corporation – 32Mx72 REGISTERED DDR SDRAM

White Electronic Designs ^{W3E32M72SR-XSBX}
VREF
A0-12
BA0-1
RESET#
CAS#
RAS#
WE#
CS#
CKE
FIG. 2 – FUNCTIONAL BLOCK DIAGRAM
CK CK#
SSTV16857
IC6
VREF
RESET#
RCK
RCK#
CK CK#
SSTV16857
IC7
VREF
RESET#
CASB#
RASB#
WEB#
CSB#
CKEB
CK0
CK0#
CKEB
DM0
DM1
DQS0
DQS1
CS# WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK#
CKE
DQML
DQMH
IC1
DQ0
Y=
Y=
Y=
Y=
Y=
Y=
DQ15
DQSL
DQSH
CSB#
WEB#
RAS B#
CASB#
DQ0
Y=
Y=
Y=
Y=
Y=
Y=
DQ15
CK1
CK1#
CKEB
DM2
DM3
DQS2
DQS3
CS# WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
IC2
DQ0
Y=
Y=
Y=
Y=
Y=
Y=
DQ15
DQ16
Y=
Y=
Y=
Y=
Y=
Y=
DQ31
CK2
CK2#
CKEB
DM4
DM5
DQS4
DQS5
CS# WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
IC3
DQ0
Y=
Y=
Y=
Y=
Y=
Y=
DQ15
DQ32
Y=
Y=
Y=
Y=
Y=
Y=
DQ47
CK3
CK3#
CKEB
DM6
DM7
DQS6
DQS7
CS# WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
IC4
DQ0
Y=
Y=
Y=
Y=
Y=
Y=
DQ15
DQ48
Y=
Y=
Y=
Y=
Y=
Y=
DQ63
CK4
CK4#
CKEB
DM8
DM9
DQS8
DQS9
CS# WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
IC5
DQ0
Y=
Y=
Y=
Y=
Y=
Y=
DQ15
DQ64
Y=
Y=
Y=
Y=
Y=
Y=
DQ79
applied after VCCQ to avoid device latch-up,
which may cause permanent damage to
the device. VREF can be applied any time
after VCCQ but is expected to be nominally
coincident with VTT. Except for CKE, inputs
are not recognized as valid until after VREF
is applied. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after
VCC is applied. After CKE passes through
VIH, it will transition to an SSTL_2 signal
and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE
during power-up is required to ensure that
the DQ and DQS outputs will be in the High-
Z state, where they will remain until driven in
normal operation (by a read access). After
all power supply and reference voltages
are stable, and the clock is stable, the DDR
SDRAM requires a 200µs delay prior to
applying an executable command.
Once the 200µs delay has been satisfied,
a DESELECT or NOP command should
be applied, and CKE should be brought
HIGH. Following the NOP command, a
PRECHARGE ALL command should be
applied. Next a LOAD MODE REGISTER
command should be issued for the extended
mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another
LOAD MODE REGISTER command to
the mode register (BA0/BA1 both LOW) to
reset the DLL and to program the operating
parameters. Two-hundred clock cycles are
required between the DLL reset and any
READ command. A PRECHARGE ALL
command should then be applied, placing
the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH
cycles must be performed (tRFC must be
satisfied.) Additionally, a LOAD MODE
REGISTER command for the mode register
with the reset DLL bit deactivated (i.e., to
program operating parameters without
resetting the DLL) is required. Following
these requirements, the DDR SDRAM is
ready for normal operation.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 3
4
White Electronic Designs Corporation • [phone] • www.wedc.com