W3E32M72SR-XSBX Datasheet, PDF (13/19 Pages) White Electronic Designs Corporation – 32Mx72 REGISTERED DDR SDRAM

White Electronic Designs ^{W3E32M72SR-XSBX}
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
Notes 1-5, 14-17, 33
Parameter
Access window of DQs from CK/CK#
CK high-level width (30)
CK low-level width (30)
Clock cycle time
CL = 2.5 (45, 51)
CL = 2 (45, 51)
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period (34)
Data-out high-impedance window from CK/CK# (18, 42)
Data-out low-impedance window from CK/CK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (43)
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
REFRESH to REFRESH command interval (23) (Commercial & Industrial only)
REFRESH to REFRESH command interval (23) (Military temperature only)*
Average periodic refresh interval (23) (Commercial & Industrial only)
Average periodic refresh interval (23) (Military temperature only)*
Terminating voltage delay to VCC (53)
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
* Self refresh available in commercial and industrial temperatures only.
Symbol
tAC
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
na
tREFC
tREFC
tREFI
tREFI
tVTD
tXSNR
tXSRD
266 MHz CL 2.5
200 CL 2
Min
-0.75
0.45
0.45
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.75
0.90
0.90
1
1
15
tHP-tQHS
40
20
65
75
20
20
0.9
0.4
15
0.25
0
0.4
15
Max
+0.75
0.55
0.55
13
13
+0.75
0.5
1.25
+0.75
0.75
120,000
1.1
0.6
0.6
1
tQH - tDQSQ
70.3
35
7.8
3.9
0
75
200
250 MHz CL2.5
200 MHz CL2
Min
-0.8
0.45
0.45
8
10
0.6
0.6
2
-0.8
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
40
20
70
80
20
20
0.9
0.4
15
0.25
0
0.4
15
Max
+0.8
0.55
0.55
13
13
+0.8
0.6
1.25
+0.8
1
120,000
1.1
0.6
0.6
1
tQH - tDQSQ
70.3
35
7.8
3.9
0
80
200
200 MHz CL2.5
150 MHz CL2
Min
-0.8
0.45
0.45
10
13
0.6
0.6
2
-0.8
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
40
20
70
80
20
20
0.9
0.4
15
0.25
0
0.4
15
Max
+0.8
0.55
0.55
13
15
+0.8
0.6
1.25
+0.8
1
120,000
1.1
0.6
0.6
1
tQH - tDQSQ
70.3
35.15
7.8
3.9
0
80
200
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
µs
µs
ns
ns
tCK
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 3
13
White Electronic Designs Corporation • [phone] • www.wedc.com