W364M72V-XSBX Datasheet, PDF (2/16 Pages) White Electronic Designs Corporation – 64Mx72 Synchronous DRAM

White Electronic Designs
W364M72V-XSBX
ADVANCED
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select
the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 4.5Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
The 4.5Gb SDRAM is designed to operate at 3.3V. An
auto refresh mode is provided, along with a power-saving,
power-down mode.
January 2005
Rev. 1
2
White Electronic Designs Corporation • [phone] • www.wedc.com