W364M72V-XSBX Datasheet, PDF (1/16 Pages) White Electronic Designs Corporation – 64Mx72 Synchronous DRAM

White Electronic Designs
W364M72V-XSBX
ADVANCED*
64Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 64M x 72
Weight: W364M72V-XSBX - TBD grams typical
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
BENEFITS
66% SPACE SAVINGS
Reduced part count from 9 to 1
Reduced I/O count
• 55% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 512MByte (4.5Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 9 chips containing
512M bits. Each chip is internally configured as a quad-
bank DRAM with a synchronous interface. Each of the
chip’s 134,217,728-bit banks is organized as 8,192 rows
by 2,048 columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
ACTUAL SIZE
25
White Electronic Designs
W364M72V-XSBX
Area = 800mm²
32
I/O Count = 219 Balls
SAVINGS – Area: 66% – I/O Count: 55%
Discrete Approach
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
22.3 ⁵⁴
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
Area: 9 x 265mm² = 2,385mm²
January 2005
Rev. 1
I/O Count: 9 x 54 pins = 486 pins
1
White Electronic Designs Corporation • [phone] • www.wedc.com