W364M72V-XSBX Datasheet, PDF (12/16 Pages) White Electronic Designs Corporation – 64Mx72 Synchronous DRAM

White Electronic Designs
W364M72V-XSBX
ADVANCED
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
-100
-125
Symbol
Min
Max
Min
Max
Unit
CL = 3
tAC
7
Access time from CLK (pos. edge)
CL = 2
tAC
7
6
ns
6
ns
Address hold time
tAH
1
1
ns
Address setup time
tAS
2
2
ns
CLK high-level width
tCH
3
3
ns
CLK low-level width
tCL
3
3
ns
Clock cycle time (22)
CL = 3
tCK
10
8
ns
CL = 2
tCK
13
10
ns
CKE hold time
tCKH
1
1
ns
CKE setup time
tCKS
2
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
1
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
2
2
ns
Data-in hold time
tDH
1
1
ns
Data-in setup time
tDS
2
2
ns
CL = 3 (10)
tHZ
7
Data-out high-impedance time
CL = 2 (10)
tHZ
7
6
ns
6
ns
Data-out low-impedance time
tLZ
1
1
ns
Data-out hold time (load) (26)
tOH
3
3
ns
Data-out hold time (no load)
tOHN
1.8
1.8
ns
ACTIVE to PRECHARGE command
tRAS
50
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
tRC
70
68
ns
ACTIVE to READ or WRITE delay
tRCD
20
20
ns
Refresh period (8,192 rows) – Commercial, Industrial
tREF
64
64
ms
Refresh period (8,192 rows) – Military
tREF
16
16
ms
AUTO REFRESH period
tRFC
70
70
ns
PRECHARGE command period
tRP
20
20
ns
ACTIVE bank A to ACTIVE bank B command
tRRD
20
20
ns
Transition time (7)
tT
0.3
1.2
0.3
1.2
ns
WRITE recovery time
(23)
1 CLK + 7ns
1 CLK + 7ns
—
tWR
(24)
15
15
ns
Exit SELF REFRESH to ACTIVE command
tXSR
80
80
ns
January 2005
Rev. 1
12
White Electronic Designs Corporation • [phone] • www.wedc.com