CMA3000-D0X Datasheet, PDF (18/35 Pages) VTI technologies – 3-axis accelerometer

CMA3000-D0X Series
‘don’t-care’ for a read operation. CMA3000 samples bits in from MOSI line on the rising edge of
SCK and bits out to MISO line on falling edge of SCK.
After the two constant '0' bits in the MISO line are the PORST status bits. All three PORST status
bits have the same value as the PORST bit in register STATUS. Bits 6 and 8 are always '0'. Bit 7 is
always ‘1’. The later 8 bits contain data for a read operation.
For write commands, data is written into the addressed register after the rising edge of CSB.
For read commands, data is latched into the internal SPI output register (shift register) on the 8th
rising edge of SCK. The output register is shifted out MSB first over MISO output.
When the CSB is high state between data transfers, the MISO line is in the high-impedance state.
4.1.2 Examples of SPI communication
4.1.2.1 Example of register read
An example of X-axis and Y-axis acceleration read command is presented in Figure 8. The master
gives the register address to be read via the MOSI line: '06' in hex format and '000110' in binary
format, register name is DOUTX). 7^th bit is set to '0' to indicate the read operation.
The sensor replies to a requested operation by transferring the register content via MISO line. After
transferring the asked DOUTX register content, the master gives next register address to be read:
'07' in hex format and '000111' in binary format, register name is DOUTY. The sensor replies to the
requested operation by transferring the register content MSB first.
CSB
SCLK
MOSI
MISO
0 00 11 0 0
PORST
000111 0
PORST
Figure 8. An example of SPI read communication.
4.1.3
Multiple slave devices in SPI bus
Since both SPI and I²C interfaces are enabled by default, certain precautions should be taken care
of when the CMA3000 is connected to a SPI bus with multiple slave devices. In case of multiple
devices on same SPI bus, it's important to prevent MOSI_SDA pin changes during SCK_SCL pin
high state. If the MOSI_SDA pin state is changed when the SCK_SCL pin is in high state, the I²C
transmission is engaged, see Figure 9 below.
Figure 9. MOSI_SDA pin change during SCK_SCL high state engages I²C transmission.
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