VG36128401A Datasheet, PDF (60/69 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM

VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Full Page Read Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE ^High
t
CK2
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t
RP
Hi-Z
DQ
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Activate
Read
Command Command
Bank A _{Bank A}
Read ^{Full page burst operation does not}
Activate
Command
Bank B
(Bank D)
Command
Bank B
(Bank D)
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
Activate
Command
Bank B
(Bank D)
Document : 1G5-0154
Rev.1
Page 60