VG36128401A Datasheet, PDF (34/69 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM

VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Power on Sequence and Auto Refresh (CBR)
CLK
CKE
CS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High level
is required
Minimum of 2 Refresh Cycles are required
tRSC
RAS
CAS
WE
BS
A10
ADD
DQM
Hi-Z
DQ
High Level is Necessary
t
RP
Precharge
Inputs ^Command
must ^{All Banks}
be stable
for 100us
1st Auto
Refresh
Command
Address Key
t
RC
2nd Auto
Refresh
Command
Mode Register Command
Set Command
Document : 1G5-0154
Rev.1
Page 34