VG36128401A Datasheet, PDF (26/69 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM

VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command. When the
precharge command is asserted, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t_RP from the precharge command.
When CAS latency is 2,the read data will remain valid until one clock after the precharge com-
mand.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge com-
mand.
Precharge Termination in READ Cycle
CLK
Command
CAS latency=2
DQ
command
CAS latency=3
DQ
Burst lengh= X
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read
Read
PRE
ACT
Q0
Q1
Q2
Q3
Hi-Z
t_RP
PRE
t_RP
Q0
Q1
Q2
Q3
ACT
Hi-Z
Document : 1G5-0154
Rev.1
Page 26