VG3617161ET Datasheet, PDF (52/69 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM

VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
CLK
CKE
CS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
CAa RBa
CBa
CBb
CBc
CAb
DQM
DQ
Hi-Z
tRCD
tRRD
tAC3
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read ^Read
Read
Command ^{Command Command}
Bank B Bank B Bank A
Precharge
Command
Bank B
Precharge
Command
Bank A
Document:1G5-0189
Rev.1
Page 52