VG3617161ET Datasheet, PDF (16/69 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM

VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
5.1 Burst Length and Sequence
(Burst Length= 2)
Starting Address
(column address A0, binary)
0
1
Sequential Addressing
Sequence (decimal)
0,1
1,0
Interleave Addressing
Sequence(decimal)
0,1
1,0
(Burst Length=4)
Starting Address
(column address A1-A0, binary)
00
01
10
11
Sequential Addressing
Sequence (decimal)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
Interleave Addressing
Sequence(decimal)
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
(Burst Length=8)
Starting Address
(column address A2-A0, binary)
000
001
010
011
100
101
110
111
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interl
eave Addressing
Sequence(decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256
words.
Document:1G5-0189
Rev.1
Page 16