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VG3617161ET Datasheet, PDF (1/69 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM | |||
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VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Description
The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed applica-
tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
⢠Single 3.3V +/- 0.3V power supply
⢠Clock frequency:166MHz, 143MHz, 125MHz
⢠Fully synchronous with all signals referenced to a positive clock edge
⢠Programmable CAS Iatency (2,3)
⢠Programmable burst length (1,2,4,8,& Full page)
⢠Programmable wrap sequence (Sequential/Interleave)
⢠Automatic precharge and controlled precharge
⢠Auto refresh and self refresh modes
⢠Dual internal banks controlled by A11(Bank select)
⢠Simultaneous and independent two bank operation
⢠I/O level : LVTTL interface
⢠Random column access in every cycle
⢠X16 organization
⢠Byte control by LDQM and UDQM
⢠4096 refresh cycles/64ms
⢠Burst termination by burst stop and precharge command
Document:1G5-0189
Rev.1
Page 1
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