VSC7126 Datasheet, PDF (12/16 Pages) Vitesse Semiconductor Corporation – 1.0625 Gbits/sec Fibre Channel Transceiver

VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Package Pin Descriptions
Figure 10: Pin Diagram
Datasheet
VSC7126
Table 4: Pin Identification
Pin #
2,4,6,9,11,14,
16,18,20,23,3,
5,8,10,12,15,
17,19,22,24
31
Name
T0:19
TBC
79
TX+
77
TX-
Description
Transmit Data Bus, Bits 0 thru 19.
INPUTS - TTL
20-bit transmit character. Parallel data on this bus is clocked in on the rising edge of
TBC. The data bit corresponding to T0 is transmitted first.
Transmit Byte Clock.
INPUT - TTL
This rising edge of this clock latches T0:9 into the input register. It also provides the
reference clock, at one twentieth of the baud rate to the PLL.
Transmitter Serial Outputs.
OUTPUTS - Differential PECL
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is
HIGH, TX+ is HIGH and TX- is LOW. (AC Coupling recommended)
Page 12
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52148-0, Rev. 4.3
3/4/99