SI9124 Datasheet, PDF (9/16 Pages) Vishay Siliconix – 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control

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Si9124
Vishay Siliconix
The pre-regulator will remain on until V_CC equals V_REG but
between V_UVLO and V_REG, excessive current may result in
V_CC falling below V_UVLO and stopping soft start operation. This
situation is avoided by the hysteresis between V_REG and
V_UVLO and correct sizing of the V_CC capacitor, bootstrap
capacitor, the soft-start capacitor, the primary MOSFET gate
driving charge, and load on the SEC_SYNC output. The value
of the V_CC capacitor should be chosen to be capable of
maintaining soft start operation with V_CC above V_UVLO until the
V_CC current can be supplied from the external circuit (e.g. via
an auxiliary winding on the secondary inductor).
V_INEXT
R_EXT = 1.4 kW
V_IN
HV_DMOS
Auxillary
V_CC
V_CC
V_REF
14.5 V
C_VCC
4.7 mF
GND
Figure 6. High-Voltage Pre-Regulator Circuit
The feedback voltage from the output of the auxiliary winding
must sustain V_CC above V_REG to fully disconnect the
pre-regulator, isolating V_CC from V_INEXT. V_CC is then
maintained above V_REG for the duration of operation. In the
event of an over voltage condition on V_CC, an internal voltage
clamp turns on at 14.5 V to shunt excessive current to GND.
In systems where operation is directly from a 12 V supply,
V_INEXT and V_CC can be connected to the 12 V bus.
The soft-start circuit is designed for the dc-dc converter to start
up in an orderly manner and reduce component stress. Soft
start is achieved by ramping the maximum achievable duty
cycle during the soft start time. The duty cycle is increased
from zero to the final value at the rate set by the an external
capacitor, C_SS as shown in Figure 7. The hiccup time is set by
an internal 20 µA current source charging C_SS from 0 V to 2
V_be, at which point switching begins. Then a 100 µA charging
current is applied to C_SS to charge from 2 V_be to the final value
controlling the duty cycle as it rises. In the event of UVLO,
shutdown or over current, the SS pin will be held low (<1 V)
disabling driver switching. A longer soft-start time may be
needed for highly capacitive loads and high peak-output
current applications. In the event of an over current condition
being detected, the soft-start pin will be pulled low and the
cycle will start again performing a hiccup as shown in Figure
4. The hiccup off-time, t₁, is given by:
t₁ [ C_SS
1.2 V
20 mA
The soft-start time t₂ is can be estimated as:
t₂
[
ǒ_CSS
(K
V_OUT n^Ǔ
100 mA)
where V_OUT is the output of the converter, and n is the turns
ratio of the primary to each secondary winding, and K is the
ratio of the resistive divider from V_INEXT to V_INDET (typically
10/1).
CS1
CS2
Blank
-
AV
+
Peak Detect
A_V 150 mV
+
GM
-
SS Enable
A_V 100 mV
V_CC
4I
I
SS Control
SS
C_SS
Document Number: 72099
S-03638—Rev. B, 20-Mar-03
Figure 7. Current-Sense and Soft-Start Circuit Block Diagram
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