SI9124 Datasheet, PDF (10/16 Pages) Vishay Siliconix – 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control

Si9124
Vishay Siliconix
New Product
Care should be taken to control the operating time using the
internal preregulator to prevent excessive power dissipation in
the IC. The use of an external dropping resistor connected in
series with the V_IN pin to drop the voltage during start up is
recommended. The value of R_EXT is selected to drop the input
voltage to the IC under worst case conditions thereby
dissipating power in the resistor, instead of the IC. If the supply
output is shorted and the auxiliary winding does not provide the
V_CC current, then continuous soft start cycles will occur. The
average power in the IC during start-up where the hiccup
operation would be performed continuously is given by:
Power (IC) + V_IN
ƪ ǒ Ǔƫ t₁ I_CC2 ) t₂ I_CC4 ) I_CC5 ) I_{SEC_SYNC}
ǒ_{t1 ) t2}Ǔ
Power ^ǒR_EXT^Ǔ + V_ID
ƪ ǒ Ǔƫ t₁ I_CC2 ) t₂ I_CC4 ) I_CC5 ) I_{SEC_SYNC}
ǒ_{t1 ) t2}Ǔ
where V_ID + ^ǒV_INEXT * V_IN^Ǔ
where I_CC2 is the non-switching supply current, I_CC4 and I_CC5
are the supply current while switching, and I_{SEC_SYNC} is the
average current out of the SEC_SYNC pin, and t₁ and t₂ are
defined in Figure 4.
After the feedback voltage from the secondary overrides the
internal pre-regulator, no current flows through R_EXT. An
example of the feedback circuitry is shown in Figure 15.
The SS pin has a predictable +1.25-mV/_C temperature
coefficient and can be used to continuously monitor the
junction temperature of the IC for a given power dissipation.
Reference
The reference voltage of Si9124 is set at 3.3 V. The reference
voltage should be de-coupled externally with a 0.1 µF
capacitor. The V_REF voltage is 0 V in shutdown mode and has
50-mA source capability.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage mode
and generates a fixed frequency pulse-width modulated signal
to the drivers. Duty cycle is controlled over a wide range to
maintain the output voltage under line and load variation.
Voltage feed-forward is also included to improve line regulation
and transient response. In the push-pull topology requiring
isolation between output and input, the reference voltage and
error amplifier must be supplied externally, usually on the
secondary side.
The error information is usually passed to the power controller
through an opto-coupling device for isolation. The error
information enters the IC via pin EP and where 0 V results in
the maximum duty cycle, whilst 2 V represents minimum duty
cycle. The EP error signal is gained up by -2.2X via an
inverting amplifier and compared against the internal ramp
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generator. The relationship between Duty Cycle and V_EP is
shown in the Typical Characteristic section, Duty Cycle vs. V_EP
at 25 _C , page 12.
Voltage feed-forward is implemented by taking the attenuated
V_INEXT signal at V_INDET to directly modulate he duty cycle. This
relationship is shown in the Typical Characteristic section,
Duty Cycle vs. V_INDET, page 12. The response time to line
transients is very short since the PWM duty cycle is charged
directly without having to go through the error amplifier
feedback loop. At start-up, i.e., once V_CC is greater than
V_UVLO, switching is initiated under soft-start control which
increases maximum attainable switch on-time linearly over the
soft-start period. Start-up from a V_INDET power down,
over-temperature, or over current is also initiated under
soft-start control.
Push-Pull and Synchronous Rectification Timing
Sequence
The PWM signal generated within the IC controls the OUT_A
and OUT_B drivers on alternate cycles. A period of inactivity
always results after initiation of the soft-start cycle until the
soft-start voltage reaches approximately 2 V_be and PWM
generated switching begins. The timing and coordination of
the drives to the primary and secondary stages is very
important and the relationships are shown in Figure 3. It is
essential to avoid the situation where both of the secondary
MOSFETs are on when either the OUT_A or OUT_B switches are
active. In this situation the transformer would effectively be
presented with a short across the output. To avoid this a timing
signal is made available which is ahead of the primary drive
outputs by 80 ns.
Primary MOSFET Drivers
The drive voltage for the primary MOSFETs is provided directly
from the V_CC and V_CC2 supply. The switch gate drive signals
OUT_A and OUT_B are shown in Figure 3. The drive currents for
the primary side MOSFETs is supplied from the V_CC and V_CC2
supply and can influence start up conditions.
Secondary Synchronization Driver
The secondary side MOSFETs are driven by the SEC_SYNC
output via a pulse transformer and gate driver circuits. The
time relationships are shown in Figure 3. Logic circuitry on the
secondary side is required to align the synchronous rectifier
gate drive with the primary drive. The current supplied to the
pulse transformer is drawn from V_CC.
Oscillator
The oscillator is designed to operate at a frequencies up to 500
kHz. The 500-kHz operating frequency allows the converter to
minimize the inductor and capacitor size, improving the power
density of the converter. The oscillator and therefore the
switching frequency is programmable by a resistor on the
R_OSC pin. The relationship is shown in the Typical
Characteristics, F_OSC vs. R_OSC.
Document Number: 72099
S-03638—Rev. B, 20-Mar-03