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DG428_11 Datasheet, PDF (8/14 Pages) Vishay Siliconix – Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
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DG428, DG429
Vishay Siliconix
SCHEMATIC DIAGRAM (Typical Channel)
V+
GND
VREF
D
EN
DO
QO
V+
V-
AX
Dn
Qn
Level
Shift
Decode/
Drive
Latches
S1
WR
CLK
V+
RESET
RS
V-
V-
TIMING DIAGRAMS
3V
WR
0V
A0, A1, (A2) 3 V
EN 0 V
50 %
tW
tS
20 %
tH
80 %
Figure 2.
Sn
Figure 1.
3V
RS
0V
VO
Switch
Output
0V
50 %
tRS
tOFF(RS)
Figure 3.
80 %
TEST CIRCUITS
+ 2.4 V
+ 15 V
V+
RS
EN
All S and Da
+5V
DG428
DG429
A0, A1, (A2)
Db, D
VO
GND WR V-
50 Ω
- 15 V 300 Ω
35 pF
Logic
3V
Input
0V
VS
Switch
Output
VO
0V
50 %
tr < 20 ns
tf < 20 ns
80 %
tOPEN
Figure 4. Break-Before-Make
www.vishay.com
Document Number: 70063
8
S11-1350–Rev. K, 04-Jul-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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