DG428_11 Datasheet, PDF (1/14 Pages) Vishay Siliconix – Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers

DG428, DG429
Vishay Siliconix
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
DESCRIPTION
The DG428, DG429 analog multiplexers have on-chip
address and control latches to simplify design in
microprocessor based applications. Break-before-make
switching action protects against momentary crosstalk of
adjacent input signals.
The DG428 selects one of eight single-ended inputs to a
common output, while the DG429 selects one of four
differential inputs to a common differential output.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up to
the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (A_x)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
The silicon-gate CMOS process enables operation over a
wide range of supply voltages. The absolute maximum
voltage rating is extended to 44 V. Additionally, single supply
operation is also allowed and an epitaxial layer prevents
latchup.
On-board TTL-compatible address latches simplify the digital
interface design and reduce board space in bus-controlled
systems such as data acquisition systems, process controls,
avionics, and ATE.
FEATURES
• Halogen-free according to IEC 61249-2-21
Definition
• Low R_DS(on): 55 
• Low Charge Injection: 1 pC
• On-Board TTL Compatible Address Latches
• High Speed - t_TRANS: 160 ns
• Break-Before-Make
• Low Power Consumption: 0.3 mW
• Compliant to RoHS Directive 2002/95/EC
BENEFITS
• Improved System Accuracy
• Microprocessor Bus Compatible
• Easily Interfaced
• Reduced Crosstalk
• High Throughput
• Improved Reliability
APPLICATIONS
• Data Acquisition Systems
• Automatic Test Equipment
• Avionics and Military Systems
• Communication Systems
• Microprocessor-Controlled Analog Systems
• Medical Instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG428
Dual-In-Line
WR 1
18 RS
A₀ 2
17 A1
EN 3
Latches
16 A₂
V- 4 ^{Decoders/Drivers} 15 GND
S₁ 5
S₂ 6
14 V+
13 S5
S₃ 7
12 S6
S₄ 8
D9
11 S₇
10 S₈
Top View
DG428
PLCC
3 2 1 20 19
EN 4
V- 5
S₁ 6
S₂ 7
S₃ 8
Latches
Decoders/Drivers
18 A₂
17 GND
16 ^V+
15 S₅
14 S₆
9 10 11 12 13
Top View
Document Number: 70063
www.vishay.com
S11-1350–Rev. K, 04-Jul-11
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000