SI8461DB Datasheet, PDF (7/8 Pages) Vishay Siliconix – P-Channel 20 V (D-S) MOSFET

www.vishay.com
Package Information
Vishay Siliconix
MICRO FOOT^®: 4-Bumps
(1 mm x 1 mm, 0.5 mm Pitch, 0.286 mm Bump Height)
4x Ø b1
Mark on backside of die
XXXX
XXX
S
S
D
G
s
e
D
b
b1
Note 5
K
Bump (Note 1)
4x 0.30 to 0.31
(Note 3)
Solder mask-0.4
e
Recommended land pattern
Notes
1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser mark on the backside surface of die.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
DIM.
A
A1
A2
b
b1
e
s
D
K
MIN.
0.458
0.214
0.244
0.297
0.210
0.920
0.029
MILLIMETERS
NOM.
0.504
0.250
0.254
0.330
0.250
0.500
0.230
0.960
0.065
Note
• Use millimeters as the primary measurement.
MAX.
0.550
0.286
0.264
0.363
0.250
1.000
0.102
MIN.
0.0180
0.0084
0.0096
0.0117
0.0083
0.0362
0.0011
INCHES
NOM.
0.0198
0.0098
0.0100
0.0130
0.0098
0.0197
0.0091
0.0378
0.0026
MAX.
0.0217
0.0113
0.0104
0.0143
0.0096
0.0394
0.0040
ECN: T15-0176-Rev. A, 27-Apr-15
DWG: 6039
Revision: 27-Apr-15
1
Document Number: 69370
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000