SI9122 Datasheet, PDF (5/17 Pages) Vishay Siliconix – 500-kHz Half-Bridge DC-DC Converter With Integrated Secondary Synchronous Rectification Drivers

Si9122
Vishay Siliconix
SPECIFICATIONS^a
Parameter
Symbol
Output MOSFET DH Driver (High-Side)
Test Conditions
Unless Otherwise Specified
f_NOM = 500 kHz, V_IN = 72 V
V_INDET = 7.2 V; 10 V v V_CC v 13.2 V
Min^b
Limits
−40 to 85_C
Typ^c
Output High Voltage
V_OH
Output Low Voltage
V_OL
Boost Current
I_BST
L_X Current
Peak Output Source
I_LX
I_SOURCE
Peak Output Sink
Rise Time
I_SINK
t_r
Fall Time
t_f
Output MOSFET DLDriver (Low-Side)
Sourcing 10 mA
Sinking 10 mA
V_LX = 72 V, V_BST = V_LX + V_CC
V_LX = 72 V, V_BST = V_LX + V_CC
V_CC = 10 V
C_DH = 3 nF
V_BST − 0.3
1.3
−1.1
0.75
1.9
−0.7
−1.0
1.0
35
35
Output High Voltage
V_OH
Output Low Voltage
V_OL
Peak Output Source
I_SOURCE
Peak Output Sink
Rise Time
I_SINK
t_r
Fall Time
t_f
Synchronous Rectifier (SRH, SRL) Drivers
Sourcing 10 mA
Sinking 10 mA
V_CC = 10 V
C_DL = 3 nF
V_CC − 0.3
0.75
−1.0
1.0
35
35
Output High Voltage
Output Low Voltage
Break-Before-Make Time^f
Peak Output Source
Peak Output Sink
Rise Time
Fall Time
Voltage Mode
V_OH
V_OL
t_BBM1
t_BBM2
t_BBM3
t_BBM4
I_SOURCE
I_SINK
t_r
t_f
Sourcing 10 mA
Sinking 10 mA
T_A = 25_C, R_BBM = 33 kW, See Figure 3
T_A = 25_C,R_BBM = 33 kW, L_X = 72 V
V_CC = 10 V
C_SRH = C_SRL = 0.3 nF
V_CC − 0.4
55
40
35
55
−100
100
35
35
Error Amplifier
Current Mode
t_d1DH
t_d2DL
Input to high-side switch off
Input to low-side switch off
t200
t200
Current Amplifier
t_d3DH
t_d4DL
Input to high-side switch off
Input to low-side switch off
t200
t200
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (−40_ to 85_C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. F_MIN when V_{CL_CONT} at clamp level. Typical foldback frequency change +20%, −30% over temperature.
e. Measured on SRL or SRH outputs.
f. See Figure 3 for Break-Before-Make time definition.
g. V_UVLO tracks V_REG1 by a diode drop
h. C_BBM may be required to reduce noise into BBM pin for non-optimum layout.
Max^b
V_LX + 0.3
2.7
−0.4
−0.75
0.3
−0.75
0.4
Unit
V
mA
A
ns
V
A
ns
V
ns
mA
ns
ns
ns
Document Number: 71815
S-41944—Rev. F, 18-Oct-04
www.vishay.com
5