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SI9122 Datasheet, PDF (10/17 Pages) Vishay Siliconix – 500-kHz Half-Bridge DC-DC Converter With Integrated Secondary Synchronous Rectification Drivers
Si9122
Vishay Siliconix
Current Limit
Current mode control providing constant current operation is
achieved by monitoring the differential voltage between the
CS1and CS2 pins which are connected across a primary
low-side sense resistor. Once this differential voltage exceeds
the 100-mV trigger point, the voltage on the CL_CONT pin is
pulled lower at a rate proportional to the excess voltage and the
value of the external capacitor connected between the
CL_CONT pin and ground. If the voltage between CS1 and CS2
exceeds 150 mV the CL_CONT capacitor is discharged rapidly
resulting in minimum duty cycle and frequency immediately.
Lowering the CL_CONT voltage results in PWM control of the
output drive being taken over by the current limit control loop.
Current control works to initially reduce the switching duty
cycle down to DMIN (12.5%). Further reduction in the duty
cycle is accompanied by a reduction in switching frequency at
a rate proportional to the duty cycle. This prevents the on time
of the primary drivers fnom from reducing below 100 ns and
avoiding a current tail. Frequency reduction occurs to a
maximum of one fifth of the nominal frequency.
With constant current mode control of on time and with
reduced operating frequency, protection of the MOSFET
switches is increased during fault conditions. Minimum duty
cycle and reduced frequency switching continues for the
duration of the fault condition. The converter reverts to voltage
mode operation immediately whenever the primary current
fails to reach the limit level. CL_CONT clamps to 6.5 V when not
in current limit.
The soft-start function does not apply under current limit as this
would constitute hiccup mode operation.
VIN Voltage Monitor –VINDET
The chip provides a means of sensing the voltage of VIN, and
withholding operation of the output drivers until a minimum
voltage of VREF (3.3 V, 300-mV hysteresis), is achieved. This
is achieved by choosing an appropriate resistive tap between
the ground and VIN, and comparing this voltage with the
reference voltage. When the applied voltage is greater than
VREF, the output drivers are activated as normal. VINDET also
provides the input to the voltage feed forward function.
However, if the divided voltage applied to the VINDET pin is
greater than VCC −0.3 V, the high-side driver, DH, will stop
switching until the voltage drops below VCC −0.3 V. Thus, the
resistive tap on the VIN divider must be set to accommodate
the normal VCC operating voltage to avoid this condition.
Alternatively, a zener clamp diode from VINDET to GND may
also be used.
Shutdown Mode
If VINDET is forced below the lower threshold, a minimum of
350 mV(VSD), the device will enter SHUTDOWN mode. This
powers down all unnecessary functions of the controller,
ensures that the primary switches are off and results in a low
level current demand from the VIN or VCC supplies.
VINEXT
VIN
(Si9122)
REXT
HVDMOS
VREF
REG_COMP
CEXT
2 nF
14.5 V
PNP Ext
Auxillary
VCC
VCC
CVCC
0.5 mF
GND
Figure 5. High-Voltage Pre-Regulator Circuit
CS1
CS2
Blank
− AV
+
Peak Detect
AV 150 mV
+ GM
−
VCC
IPU
120 mA (nom)
AV
OSC
VOFFSET
CL_CLAMP
CL_CONT
REXT
AV 100 mV
+ GM
−
IPD
0 − 240 mA (nom)
CEXT
Figure 6 . Current Limit Circuit
www.vishay.com
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Document Number: 71815
S-41944—Rev. F, 18-Oct-04