DG3157A Datasheet, PDF (4/7 Pages) Vishay Siliconix – Low Voltage, 300-MHz - 3 dB Bandwidth, SPDT Analog Switch with Power Down Protection (2:1 Multiplexer/Demultiplexer Bus Switch)

DG3157A, DG3157B
Vishay Siliconix
LOGIC DIAGRAM Positive Logic
B₁
1
S
6
B₀
3
4
A
AC LOADING AND WAVEFORMS
From Output
Under Test
C_L
50 pF
Figure 1.
R_L
500 Ω
R_L
500 Ω
V_LD
SW
Open
GND
TEST
t_PLH/t_PHL
t_PLZ/t_PZL
t_PHZ/t_PZH
SW
Open
V_LD
GND
Load Circuit
Figure 2. AC Test Circuit
t_r = 2.5 ns
Switch
Input
10 %
90 %
50 %
90 %
50 %
t_w
t _{PL H}
Output
50 %
t_f = 2.5 ns
V+
t_f = 2.5 ns
90 %
Logic
Input
50 %
10 %
GND
10 %
t _{PZ L}
10 %
t _{PH L}
V_OH
50 %
Output
Waveform 1
SW at V_LD
t _{PZ H}
50 %
V_OL
Output
Waveform 2
SW at GND
50 %
t_r = 2.5 ns
V+
90 %
50 %
GND
t _{PL Z}
V_LD
2
V_OL + 0.3 V
V_OL
t _{PH Z}
V_OH
V_OH 0.3 V
0V
Propagation Delay Times
Enable and Disable Time-Low- and High-Level Enabling
Figure 3. AC Waveforms
Notes:
• C_L includes probe and jig capacitance.
• Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
• Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
• All input pulses are supplied by generators having the following characteristics: Input PRR = 1.0 MHz, t_w = 500 ns.
• The outputs are measured one at a time with one transition per measurement.
• V_LD = 2 V+.
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4
Document Number: 68628
S-81944-Rev. C, 25-Aug-08