DG221B Datasheet, PDF (4/6 Pages) Vishay Siliconix – Quad SPST CMOS Analog Switch with Latches

DG221B
Vishay Siliconix
New Product
TEST CIRCUITS
+15 V
V+
2V
S
D
3V
Logic
Input
V_O
0V
IN
GND WR V–
–15 V
R_L
1 kW
C_L
35 pF
Switch
Input
V_S
Switch
Output
V_O
C_L (includes fixture and stray capacitance)
V_O = V_S
R_L
R_L + r_DS(on)
FIGURE 2. Switching Time
50%
t_r < 10 ns
t_f < 10 ns
90%
t_ON
t_OFF
+15 V
0V
WR
V+
S
D
2V
V_O
IN
GND
R_L
C_L
V–
1 kW
35 pF
–15 V
C_L (includes fixture and stray capacitance)
3V
WR
0V
3V
IN
0V
V_S
V_OUT
V_O
t_ON, WR
50%
90%
V_O = V_S
R_L
R_L + r_DS(on)
FIGURE 3. WR Switching Time
t_r < 10 ns
t_f < 10 ns
t_OFF , WR
3V
IN
3V
WR
VOUT
50%
t_S
t_H
t_S
t_H
50%
t_W
t_H = Hold Time
t_S = Setup Time
t_W = WR Pulse Width
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4
The latches are level sensitive. When WR is held low the latches are transparent and the switches re-
spond to the digital inputs. The digital inputs are latched on the rising edge of WR.
FIGURE 4. WR Setup Conditions
Document Number: 71616
S-03627—Rev. A, 23-Apr-01