VS-P100 Datasheet, PDF (2/8 Pages) Vishay Siliconix – Power Modules, Passivated Assembled Circuit Elements, 25 A

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VS-P100 Series
Vishay Semiconductors
ON-STATE CONDUCTION
PARAMETER
Maximum DC output current at case
temperature
Maximum peak, one-cycle non-repetitive
on-state or forward current
Maximum I²t for fusing
Maximum I²ïƒ–t for fusing
Maximum value of threshold voltage
Maximum level value of on-state slope
resistance
Maximum on-state voltage drop
Maximum forward voltage drop
Maximum non-repetitive rate of rise of
turned-on current
Maximum holding current
Maximum latching current
SYMBOL
I_O
I_TSM,
I_FSM
I²t
I²ïƒ–t
V_T(TO)
r_t1
V_TM
V_FM
dI/dt
I_H
I_L
TEST CONDITIONS
Full bridge
t = 10 ms
t = 8.3 ms
No voltage
reapplied
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
100 % V_RRM
reapplied
No voltage
reapplied
Sinusoidal half wave,
initial T_J = T_J maximum
t = 10 ms
t = 8.3 ms
100 % V_RRM
reapplied
t = 0.1 ms to 10 ms, no voltage reapplied
I²t for time tx = I²ïƒ–t · tx
T_J = 125 °C
VALUES
25
85
357
375
300
315
637
580
450
410
6365
0.82
T_J = 125 °C, average power = V_T(TO) x I_T(AV) + r_t + (I_T(RMS))²
12
I_TM =  x I_T(AV)
T_J = 25 °C
I_FM =  x I_F(AV)
T_J = 25 °C
T_J = 125 °C from 0.67 V_DRM
I_TM =  x I_T(AV), I_g = 500 mA, t_r < 0.5 μs, t_p > 6 μs
T_J = 25 °C anode supply = 6 V, resistive load, gate open
T_J = 25 °C anode supply = 6 V, resistive load
1.35
1.35
200
130
250
UNITS
A
°C
A
A²s
A²ïƒ–s
V
m
V
V
A/μs
mA
BLOCKING
PARAMETER
Maximum critical rate of rise of off-state
voltage
Maximum peak reverse and off-state
leakage current at V_RRM, V_DRM
Maximum peak reverse leakage current
RMS isolation voltage
SYMBOL
TEST CONDITIONS
dV/dt
I_RRM,
I_DRM
I_RRM
V_ISOL
T_J = 125 °C, exponential to 0.67 V_DRM gate open
T_J = 125 °C, gate open circuit
T_J = 25 °C
50 Hz, circuit to base, all terminals shorted, 
T_J = 25 °C, t = 1 s
VALUES
200
UNITS
V/μs
10
mA
100
μA
2500
V
TRIGGERING
PARAMETER
Maximum peak gate power
Maximum average gate power
Maximum peak gate current
Maximum peak negative gate voltage
SYMBOL
P_GM
P_G(AV)
I_GM
-V_GM
Maximum gate voltage required to trigger
V_GT
Maximum gate current required to trigger
I_GT
Maximum gate voltage that will not trigger V_GD
Maximum gate current that will not trigger
I_GD
TEST CONDITIONS
T_J = - 40 °C
T_J = 25 °C
T_J = 125 °C
T_J = - 40 °C
T_J = 25 °C
T_J = 125 °C
Anode supply =
6 V resistive load
T_J = 125 °C, rated V_DRM applied
VALUES
8
2
2
10
3
2
1
90
60
35
0.2
2
UNITS
W
A
V
V
mA
V
mA
Revision: 27-Mar-14
2
Document Number: 93754
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