SI4953DY Datasheet, PDF (2/4 Pages) Fairchild Semiconductor – Dual P-Channel Enhancement Mode MOSFET

Si4953DY
Vishay Siliconix
SPECIFICATIONS (T_J = 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current^b
Drain-Source On-State Resistance^b
Forward Transconductance^b
Diode Forward Voltage^b
Dynamic^a
V_GS(th)
I_GSS
I_DSS
I_D(on)
r_DS(on)
g_fs
V_SD
V_DS = V_GS, I_D = - 250 mA
V_DS = 0 V, V_GS = "20 V
V_DS = - 30 V, V_GS = 0 V
V_DS = - 30 V, V_GS = 0 V, T_J = 55_C
V_DS v - 5 V, V_GS = - 10 V
V_GS = - 10 V, I_D = - 4.9 A
V_GS = - 4.5 V, I_D = - 3.6 A
V_DS = - 15 V, I_D = - 4.9 A
I_S = - 1.7 A, V_GS = 0 V
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q_g
Q_gs
Q_gd
R_g
t_d(on)
t_r
t_d(off)
t_f
t_rr
Notes
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width v 300 ms, duty cycle v 2%.
V_DS = - 15 V, V_GS = - 10 V, I_D = - 4.9 A
V_DD = - 15 V, R_L = 15 W
I_D ^ - 1 A, V_GEN = - 10 V, R_G = 6 W
I_F = - 1.7 A, di/dt = 100 A/ms
Min Typ^a Max Unit
-1
V
"100
nA
-1
mA
- 25
- 20
A
0.043
0.053
W
0.070
0.095
10
S
0.8
- 1.2
V
16
25
5
nC
2
2
7.1
W
9
15
13
20
25
40
ns
15
25
60
90
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Document Number: 70153
S-31726—Rev. E, 18-Aug-03