SI7938DP Datasheet, PDF (10/13 Pages) Vishay Siliconix – Dual N-Channel 40-V (D-S) MOSFET

AN821
Vishay Siliconix
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθ_jc, or the
junction-to-foot thermal resistance, Rθ_jf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the DPAK, PowerPAK SO-8, and stan-
dard SO-8. The PowerPAK has thermal performance
equivalent to the DPAK, while having an order of magni-
tude better thermal performance over the SO-8.
Because of the presence of the trough, this result sug-
gests a minimum performance improvement of 10 °C/W
by using a PowerPAK SO-8 in a standard SO-8 PC
board mount.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no
traces running between the body of the MOSFET.
Where the standard SO-8 body is spaced away from the
pc board, allowing traces to run underneath, the Power-
PAK sits directly on the pc board.
Thermal Performance - Spreading Copper
TABLE 1.
DPAK and PowerPAK SO-8
Equivalent Steady State Performance
DPAK
PowerPAK
SO-8
Thermal
Resistance Rθ_jc
1.2 °C/W
1.0 °C/W
Standard
SO-8
16 °C/W
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pat-
tern. The question then arises as to the thermal perfor-
mance of the PowerPAK device under these conditions.
A characterization was made comparing a standard SO-8
and a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The
results are shown in Figure 5.
Designers may add additional copper, spreading cop-
per, to the drain pad to aid in conducting heat from a
device. It is helpful to have some information about the
thermal performance for a given area of spreading cop-
per.
Figure 6 shows the thermal resistance of a PowerPAK
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4
PC board. The two internal layers and the backside layer
are solid copper. The internal layers were chosen as
solid copper to model the large power and ground
planes common in many applications. The top layer was
cut back to a smaller area and at each step junction-to-
ambient thermal resistance measurements were taken.
The results indicate that an area above 0.3 to 0.4 square
inches of spreading copper gives no additional thermal
performance improvement. A subsequent experiment
was run where the copper on the back-side was
reduced, first to 50 % in stripes to mimic circuit traces,
and then totally removed. No significant effect was
observed.
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
60
R_th vs. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
56
50
40
Si4874DY
30
Si7446DP
20
10
0
0.0001
0.01
1
100
Pulse Duration (sec)
10000
Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path
51
46
41
100 %
0%
50 %
36
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper Junction-to-Ambient Performance
Document Number 71622
28-Feb-06
www.vishay.com
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