PI3420-00-LGIZ Datasheet, PDF (23/30 Pages) Vicor Corporation – 8 V to 18 Vin, 15 A Cool-Power ZVS Buck Regulator

Output Overvoltage Protection
The PI34xx-00 family is equipped with output Overvoltage
Protection (OVP) to prevent damage to input voltage
sensitive devices. If the output voltage exceeds 20% of its set
regulated value, the regulator will complete the current cycle,
stop switching and issue an OVP fault. The system will
resume operation once the output voltage falls below the
OVP threshold and after Fault Restart Delay.
Overtemperature Protection
The internal package temperature is monitored to prevent
internal components from reaching their thermal maximum.
If the Over Temperature Protection Threshold (OTP) is
exceeded (T_OTP), the regulator will complete the current
switching cycle, enter a low power mode, set a fault flag, and
will soft-start when the internal temperature falls below Over-
Temperature Restart (T_{OTP_HYS}).
Parallel Operation
Paralleling modules can be used to increase the output
current capability of a single power rail and reduce output
voltage ripple.
V_IN
C_IN
R1
SYNCO(#2)
SYNCI(#2)
EN(#2)
EAO(#2)
TRK(#2)
V_IN
PGND
L1
VS1
V_OUT
ZVS Buck
PGD _(#1) REM
SYNCI
SYNCO
EN
EAO
TRK
SGND
C_OUT
V_IN
C
IN
SYNCO(#1)
SYNCI(#1)
EN(#1)
EAO(#1)
TRK(#1)
L1
V_IN
VS1
PGND
V_OUT
ZVS Buck
PGD _(#2) REM
SYNCI
SYNCO
EN
EAO
TRK
SGND
C
OUT
V_OUT
Figure 37 — PI34xx-00 parallel operation
By connecting the EAO pins and SGND pins of each module
together the units will share the current equally. When the
TRK pins of each unit are connected together, the units will
track each other during soft-start and all unit EN pins have to
be released to allow the units to start (See Figure 37). Also,
any fault event in any regulator will disable the other
regulators. The two regulators will be out of phase with each
other reducing output ripple (refer to Switching Frequency
Synchronization).
To provide synchronization between regulators over the
entire operational frequency range, the Parallel Good (PGD)
pin must be connected to the lead regulator’s (#1) SYNCI pin
and a 2.5 kΩ Resistor, R1, must be placed between SYNCO
(#2) return and the lead regulator’s SYNCI (#1) pin, as shown
in Figure 37. In this configuration, at system soft-start, the
PGD pin pulls SYNCI low forcing the lead regulator to
Cool-Power^®
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Rev 1.3
12/2015
PI34xx-00
initialize the open-loop startup synchronization. Once the
regulators reach regulation, SYNCI is released and the system
is now synchronized in a closed-loop configuration which
allows the system to adjust, on the fly, when any of the
individual regulators begin to enter variable frequency mode
in the loop.
Pulse Skip Mode (PSM)
PI34xx-00 features a PSM to achieve high efficiency at light
loads. The regulators are setup to skip pulses if EAO falls
below a PSM threshold. Depending on conditions and
component values, this may result in single pulses or several
consecutive pulses followed by skipped pulses. Skipping
cycles significantly reduces gate drive power and improves
light load efficiency. The regulator will leave PSM once the
EAO rises above the Skip Mode threshold.
Variable Frequency Operation
Each PI34xx-00 is preprogrammed to a base operating
frequency, with respect to the power stage inductor (see
Table 4), to operate at peak efficiency across line and load
variations. At low line and high load applications, the base
frequency will decrease to accommodate these extreme
operating ranges. By stretching the frequency, the ZVS
operation is preserved throughout the total input line voltage
range therefore maintaining optimum efficiency.
Application Description
Output Voltage Trim
The PI34xx-00 family of Buck Regulators provides five
common output voltages: 1.0 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V. A
post-package trim step is implemented to offset any resistor
divider network errors ensuring maximum output accuracy.
With a single resistor connected from the ADJ pin to SGND or
REM, each device’s output can be varied above or below the
nominal set voltage (the PI3420-00 can only be adjusted
above the set voltage of 1 V).
Device
PI3420-00-LGIZ
PI3421-00-LGIZ
Output Voltage
Set
Range
1.0 V
1.0 to 1.4 V
1.8 V
1.4 to 2.0 V
PI3422-00-LGIZ
PI3423-00-LGIZ
PI3424-00-LGIZ
2.5 V
3.3 V
5.0 V
2.0 to 3.1 V
2.3 to 4.1 V
3.3 to 6.5 V
Table 2 — PI34xx-00 family output voltage ranges
The remote pin (REM) should always be connected to the
V_OUT pin to prevent an output voltage offset. Figure 38 shows
the internal feedback voltage divider network.
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