PRM48BF480T400B00 Datasheet, PDF (17/22 Pages) Vicor Corporation – High Efficiency Remote Sense PRM Converter

9.2.2 Setting the output current limit and overcurrent
protection level
The current limit and overcurrent protection set points
are linked, and scale together against the current sense
shunt, and the gain of the current sense amplifier. The
output of the current sense IC provides the IF voltage
which has V_{IF_IL} and V_{IF_OC} thresholds for the two
functions respectively. The set points are therefore
defined by:
I = ^{VIF _ IL}
IL
R
S
⋅ ^G _CS
and
I _OC
=
V_{IF _ OC}
R_S ⋅G_CS
where G_CS is the gain of the current sense amplifier.
9.2.3 Control loop compensation requirements
In order to properly compensate the control loop, all
components which contribute to the closed loop
frequency response should be identified and understood.
Figure 25 shows the AC small signal model for the
module. Modulator DC gain G_PR and powertrain
equivalent resistance r_{EQ_OUT} are shown. These
modeling parameters will support a design cut-off
frequency up to 50 kHz.
Standard Bode analysis should be used for calculating
the error amplifier compensation and analyzing the
closed loop stability. The recommended stability criteria
are as follows:
1) Phase Margin > 45º : for the closed loop response,
the phase should be greater than 45º where the gain
crosses 0dB.
2) Gain Margin > 10 dB : The closed loop gain should be
lower than -10dB where the phase crosses 0º.
3) Gain Slope = -20 dB/decade : The closed loop gain
should have a slope of -20 dB/decade at the crossover
frequency.
The compensation characteristics must be selected to
meet these stability criteria. Refer to Figure 27 for a
local sense, voltage-mode control example based on the
configuration in Figure 26. In this example, it is assumed
that the maximum crossover frequency (F_CMAX) has been
selected to occur between B and C. Type-2
compensation (Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
 Modulator Gain G_PR: See Figures 17, 18, 19
PRM48BF480T400B00
 Powertrain equivalent resistance r_EQ: See
Figures 17, 18, 19
 Internal output capacitance: see Figure 20
 External output capacitance value
In the case of ceramic capacitors, the ESR can be
considered low enough to push the associated zero well
above the frequency of interest. Applications with high
ESR capacitor may require a different type of
compensation, or cascade control.
The system poles and zeros of the closed loop can then
be defined as follows:
 Powertrain pole, assuming the external
capacitor ESR can be neglected:
r_{EQ _ OUT} · R_LOAD
R << _{r + R COUT _ EXT}
EQ _ OUT
LOAD
 Main pole frequency:
( ) ^{FP ≈} _{2 πâ‹} ^rEQ _ OUT ^{· RLOAD}
1
·
C
OUT
r + R _{EQ _ OUT}
LOAD
INT ^{+ C}OUT
EXT
 Compensation Mid-Band Gain:
R
G _MB
=
20 log
3
R₁
[1]
 Compensation Zero:
1
F_Z1 = _{2 π⋅ R 3 ⋅ C1}
[2]
 Compensation Pole:
F_{P 2}
=
2 π⋅
1
R₃ ⋅ C₁
⋅ C₂
C₁ + C₂
and for F_P2>>F_Z1 (C₁ + C₂ ≈ C₁):
F
P2
≈ _2π
1
⋅R
⋅ C₂
[3]
PRM® Regulator
Rev 1.1
800 927.9474