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BCM4414XD1E5135YZZ Datasheet, PDF (11/41 Pages) Vicor Corporation – Isolated Fixed-Ratio DC-DC Converter
BCM4414xD1E5135yzz
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported.
• PMBusTM command compatible.
• The internal µC requires the use of a flip-flop to drive SSTOP. See system diagram section for more details.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
Electrical Parameters
VIH
VVDD_IN = 3.3V
2.1
Input Voltage Threshold
VIL
VVDD_IN = 3.3V
VOH
VVDD_IN = 3.3V
3
Output Voltage Threshold
VOL
VVDD_IN = 3.3V
Leakage current
ILEAK_PIN Unpowered device
Signal Sink Current
ILOAD
VOL = 0.4V
4
Signal Capacitive Load
CI
Total capacitive load of
one device pin
Signal Noise Immunity
VNOISE_PP 10MHz to 100MHz
300
Timing Parameters
Operating Frequency
FSMB
Idle state = 0Hz
10
Free time between
Stop and Start Condition
tBUF
1.3
DIGITAL
Regular
INPUT/OUTPUT
Operation
Hold time after Start or
Repeated Start condition
tHD:STA
First clock is generated
after this hold time
0.6
Repeat Start Condition
Setup time
tSU:STA
0.6
Stop Condition setup time
tSU:STO
0.6
Data Hold time
tHD:DAT
300
Data Setup time
tSU:DAT
100
Clock low time out
tTIMEOUT
25
Clock low period
tLOW
1.3
Clock high period
tHIGH
0.6
Cumulative clock low
extend time
tLOW:SEXT
Clock or Data Fall time
tF
Measured from
(VIL_MAX 0.15) to (VIH_MIN + 0.15)
20
Clock or Data Rise time
tR
0.9 • VVDD_IN_MAX to (VIL_MAX 0.15)
20
TYP MAX UNIT
V
0.8 V
V
0.4 V
10 µA
mA
10 pF
mV
400 KHz
µs
µs
µs
µs
ns
ns
35 ms
µs
50 µs
25 ms
300 ns
300 ns
SCL
VIH
VIL
tLOW tR
SDA
VIH
VIL
tBUF
P
S
tHD,STA
tHD,DAT
tF
tHIGH
tSU,DAT
tSU,STA
S
tSU,STO
P
BCM® in a VIA Package
Page 11 of 41
Rev 1.4
09/2016
vicorpower.com
800 927.9474