FX-400-EAE-K Datasheet, PDF (5/9 Pages) Vectron International, Inc – Low Jitter Frequency Translator

Pin Configuration
Figure 6. Pin Configuration
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
SEL0
SEL1
GND
VMON
OD
GND
FOUT
CFOUT
LD
GND
GND
Table 7. Pin Functions
I/O
Level
I
LVCMOS
Frequency Select ^* (See Table 8)
Function
I
GND
LVCMOS
Supply
Frequency Select ^* (See Table 8)
Case and Electrical Ground
Not present
O
I
LVCMOS
GND
Supply
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input frequency may
be out of range if the voltage exceeds these levels
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Case and Electrical Ground
O
O
O
GND
LCPECL. LVDS or
LVCMOS
LVPECL, LVDS or
LVCMOS
LVCMOS
Supply
Frequency Output
Complementary Frequency Output – Note for LVCMOS option this pad will be tied to
GND.
Lock Detect
Locked = Logic “1”
Loss of Signal = Logic “0”
Case and Electrical Ground
GND
Supply
Case and Electrical Ground
13
FIN
I
LVCMOS or
Input Frequency – AC Coupled
LVPECL
14
VCC
VCC
Supply
Power Supply Voltage (3.3 V ±5%)
* _{For applications requiring two to four input frequencies, Vectron will assign a unique part number and the Input Frequency versus SEL[1:0] settings will be pro-}
vided in a Specification Control Drawing. For single input configurations it is recommended that SEL0 and SEL1 are tied to ground.
SEL0
0
0
1
1
SEL1
0
1
0
1
Table 8. Control Logic (LVCMOS)
Reference Clock Input
F
1
F
2
F
3
F
4
Page 5 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 01Apr2009