UR5595 Datasheet, PDF (8/12 Pages) Unisonic Technologies – DDR TERMINATION REGULATOR

UR5595
MOS IC
„ TYPICAL APPLICATION CIRCUITS(Cont.)
Figure 3 illustrate another application that the power rails are split when power dissipation or efficiency are
concerned. The output stage (PV_IN) can be as lower as 1.8V, and the analog circuitry (AV_IN) can be connected to a
higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current
from V_TT, but the disadvantage of this circuit is the maximum continuous current is reduced.
Figure 3. Lower Power Dissipation SSTL-2 Implementation
The third optional application is that PV_IN connect to 3.3V and AV_IN will be always limited to operation on the 3.3V
or 5V to always equal or higher than PV_IN. This configuration has the ability to provide the maximum continuous
output current at the downside of higher thermal dissipation. The power dissipation increasing problem must be
careful to prevent the junction temperature to exceed the maximum ranting. Because of this risk it is not
recommended to supply the output stage with a voltage higher than a nominal 3.3V rail.
Figure 4. SSTL-2 Implementation with higher voltage rails
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