 English |
|
|
|
|
|
|
|
| UR5595 Datasheet, PDF (7/12 Pages) Unisonic Technologies – DDR TERMINATION REGULATOR | |||
| |||
| ◁ |
UR5595
MOS IC
 TYPICAL APPLICATION CIRCUITS
Following demonstrate several different application circuits to illustrate some of the options that are possible in
configuring the UTC UR5595. The individual circuit performance can be found in the Typical Performance
Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AVIN and PVIN.
STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME
SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination
scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered
with DDR-SDRAM. The most popular form of termination is Class II single parallel termination. It involves one RS
series resistor from the chipset to the memory and one RT termination resistor (refer to Figure 1). RS and RT are
changeable to meet the current requirement from UR5595, the recommended values both RS and RT are 25Ω.
Figure 1. SSTL-Termination Scheme
FOR SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all
the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and
component count and selection.
Figure 2. Recommended SSTL-2 Implementation
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
7 of 12
QW-R502-062,A
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese